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8b-TO-10b-Encoder
- Encoder to create TLP s for data trasmission.
8B10B
- 8b/10b编解码实现，很实用。可以借鉴-8b/10b encoding and decoding to achieve, very practical. Can learn
8b10_enc
- This program is used to do encoding according to 8B/10B protocol. The program has been written in VHDL
encode_8B10B
- 用verilog编写的8B/10B编码模块。参考了网上的源码，并取消了时序，以纯逻辑实现。将3B/4B、5B/6B两部分单独写成模块，可读性更强-Using verilog 8B/10B encoding module. Online reference source, and canceled the timing, pure logic implementation. The 3B/4B, 5B/6B written two separate modules, more readable
af-phy-0039.000.pdf
- This document describes a number of enhancements to the Universal Test & Operations PHY Interface for ATM (UTOPIA) data path interface [1]. This document assumes familiarity with the Level 1 Utopia document [1], which specifies the following :
a-design-of-8b_10bSerDes
- 。论文首先给出了8b／10bSerDes的系 统结构，将其分为发送端和接收端两个部分，然后按照功能的不同，对电路进 行了模块划分，并且设计了其中的4个主要模块．8b／10b编码模块、8b／10b解码 模块、10：1并串转换模块和1：10串并转换模块。-A Design of 8b／1 0bSerDes
decoder-SerDes
- 介绍了8b/10b SerDes 中数字模块的设计和验证，这些数字模块 包括：8b/10b 编解码器、Comma 检测器和串并/并串转换电路。-This article introduces theories and applications of four types of SerDes architecture, and establishes the design of 8b/10b SerDes interface circuit through a top-down des
HIGH-8B_10B-DECODE-ASIC
- 本文重点研究了高速8b／10b解码器的设计与实现，在详细介绍了解码原理及 多种传统解码方案的基础上，采用流水线结构设计了高速8b／10b解码器。通过 仔细分析传统解码器的不足，精心设计流水线结构及触发器在关键路径上的插入 点，使得所设计电路的速度比传统解码器有了较大的提升。-This paper focuses on the 8b／l 0b decoder，including the decoding principles and a variety of decoding sc
test
- 8B/10B编码程序，注解比较详细的，verilog hdl语言。-8B/10B encoding process, more detailed notes, verilog hdl language.
aurora_8b10b_0_example.xpr
- xilinx aurora 8b\10b编码例子-xilinx aurora 8b\10 example
8B-10B
- 8b10bencode bianmaqi -8b10bencode bianmaqi jiemaqi
8b10b_encdec_latest.tar
- this a vhdl code to simulate 8b/10b encoder and decoder with a test bench-this is a vhdl code to simulate 8b/10b encoder and decoder with a test bench
ASI
- 异步串行接口ASI,QUARTUS cv demo参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI, QUARTUS cv demo reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
ASI_simulation
- 异步串行接口ASI仿真设计,quartus modelsim 仿真参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI simulation design, quartus modelsim simulation reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
8b10b_endecode
- 8b转10b的编码和解码程序，已验证。ALTERA官方代码，有编码和解码两个文件-an 8b10b decoder, based on files Martin R and IBM paper
X4_8B10B
- 4倍转换率的8b转10b的编码和解码程序，已验证。ALTERA官方代码，有编码和解码两个文件-8b 4 times the conversion rate of turn 10b encoding and decoding procedures have been verified. ALTERA official code, encoding and decoding two files
8b10b
- ALERA fpga 8B10B转换源码，用于实现8B转10B，10B转8B功能。(ALTERA fpga 8B10B conversion source, used to achieve 8B to 10B, 10B to 8B function)
gtx_aurora_zc706_example
- Aurora 8B/10B协议是Xilinx公司针对高速传输开发的一种可裁剪的轻量级链路层协议，通过一条或多条串行链路实现两设备间的数据传输。协议Aurora协议可以支持流和帧两种数据传输模式，以及全双工、单工等数据通信方式。(The Aurora 8B / 10B protocol is a tailor-made lightweight link layer protocol developed by Xilinx for high-speed transmission that enabl